The invention relates to an electronic circuit configuration having two lines and a detector device that is allocated to the two lines. The electronic circuit configuration detects a potential difference on the lines and controls a change in the line potentials in response to this.
Such a circuit configuration is used, in particular, in synchronous dynamic semiconductor memories of the random access type (SDRAM), for example when reading an SDRAM memory cell in which a potential difference on paired complementary lines needs to be assessed. In this case, the paired lines, which are connected to a sense amplifier (SA) for the memory cell, are firstly precharged to a predetermined reference-ground potential. To assess the data content, the sense amplifier is connected to the memory cells via paired complementary lines, and, depending on the data content, one of the two complementary lines is discharged. The potential difference produced between the two complementary lines as a result of one of the lines discharging is assessed by a secondary sense amplifier (SSA). After the assessment, the data content is output in amplified form via outputs of the secondary sense amplifier. After this procedure, the two complementary lines are precharged to the reference-ground potential again for the next read cycle. This charging process is faster the smaller the extent to which one of the two complementary lines was discharged. Limiting the discharge of the complementary lines produces a shorter waiting time in the charging procedure for the complementary lines and thus, in principle, results in faster read procedures.
In a previously used circuit configuration, two different approaches were used for limiting the discharge of the complementary lines during the assessment process. First, the connection between the complementary lines and the upstream sense amplifier was interrupted as soon as the potential difference state of the lines had been assessed by the secondary sense amplifier, but this meant intervening in the control of the read cycle. Second, the discharging of the complementary line was limited to a particular potential locally at the secondary sense amplifier SSA. This was achieved by coupled differential amplifiers, which limit the potential difference on the complementary lines, but these entail comparatively high circuit complexity.
It is accordingly an object of the invention to provide an electronic circuit configuration which overcomes the above-mentioned disadvantages of the prior art devices of this general type, whose circuitry is significantly simplified.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electronic circuit configuration, including two lines; a detector device connected to the two lines for detecting a potential difference on the two lines and controls a chance in line potentials in response to the potential difference; and switches coupled to a reference-ground potential, each of the two lines connected to one of the switches and the switches are connected to and driven by the detector device and, after being actuated by the detector device, each of the switches connects a potential of an associated line of the two lines to the reference-ground potential.
The object is achieved by the circuit configuration in that the complementary lines are allocated a switch which is driven by the detector device and, after actuation by the detector device, connects the potential of the respective complementary line to a reference-ground potential, which is coupled to the switch, as soon as the potential difference has been assessed by the detector device. In this way, the discharge of the complementary line is minimized and hence the time interval until further assessment can take place is reduced. This produces significantly faster read procedures.
In a particularly preferred development of the invention, the switches for charging the complementary lines are formed of terminal transistors whose gate connections or base connections are driven by the detector device and whose electrode connections (collector and source, emitter and drain) are coupled firstly to the associated line and secondly to the reference-ground potential (VCC). The advantage of this is that, in total, only two further transistors are necessary and the high circuit complexity of differential amplifiers is dispensed with, which results in a considerable saving in area on the wafer.
According to a further preferred embodiment of the invention, the detector device for the potential difference on the two complementary lines is formed by a signal memory circuit (latch circuit) whose inputs are coupled to the two complementary lines and whose outputs are coupled directly to the control connections (gates) of the switches, which apply a reference-ground potential to the complementary lines. Hence, the switches represent merely a slight addition to the standard circuit, therefore, the circuit configuration can be produced very inexpensively.
According to a particularly preferred embodiment of the invention, in which the circuit is used in a synchronous dynamic semiconductor memory of the random access type (SDRAM), a large cost saving can be achieved by dispensing with the differential amplifiers.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an electronic circuit configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.